Quelltext der Seite PEEDI Configuration (i.MX 27)

The PEEDI JTAG supports the CM-i.MX27 core module.

If you want to use the PEEDI JTAG, be sure that no software has executed before on the processor, otherwise PEEDI will not be able to connect. So, set the boot mode to '''0000''' (UART/USB bootstrapping). This way, nothing from flash is executed.

You will see the following in the PEEDI terminal:
 ++ info: RESET and TRST asserted
 ++ info: TRST released
 -- error: wrong number of TAP controller(s): detected = 0, config = 2
 ++ info: BYPASS check failed
 
 ++ info: RESET released, trying again
 ++ info: BYPASS check passed
 ++ info: 2 TAP controller(s) detected
 ++ info: TAP 0 : IDCODE = 0x07926121, Freescale i.MX27 -> CORE0
 ++ info: TAP 1 : IDCODE = 0x1B900F0F, ARM ETB
 Configuring for CM-i.MX27...
 
 Set clocks...
 
 
 Configure DDR...
 
 
 0xA0000F00: 0x00000000 0x00000000 0x00000000 0x00000000
 
 0xA0000F00: 0x00000000 0x00000000 0x00000000 0x00000000
 
 0xA0000F00: 0x00000000 0x00000000 0x00000000 0x00000000
 
 0xA0000033: 0x00
 
 0xA1000000: 0x00
 Initialization complete.
 
 ++ info: core 0: initialized

The following is an example configuration for PEEDI when used with the CM-i.MX27.

<pre>
[DEBUGGER]
PROTOCOL = gdb_remote               ; gdb remote
REMOTE_PORT = 2000                  ; TCP/IP port
GDB_READ_INGNORE_TIME = 3000        ; time in ms

[TARGET]
PLATFORM = ARM

[PLATFORM_ARM]
JTAG_CHAIN = 4, 4                   ; list of IR lenghts of all TAP controller in JTAG chain
JTAG_CLOCK = 5, 10000               ; JTAG Clock in [kHz] - 5kHz jtag clock for init operations and 10MHz for normal work
                                    ; Valid range: 5 - 33000
TRST_TYPE = PUSHPULL                ; type of TRST output: OPENDRAIN or PUSHPULL
WAKEUP_TIME = 3000                  ; time between releasing the reset and starting the jtag communication
RESET_TIME = 500                    ; lenght of RESET pulse in ms; 0 means no RESET

CORE0 = ARM926E, 0                  ; TAP 0 is ARM926E  CPU
CORE0_STARTUP_MODE      = RESET     ; startup mode after reset:
                                    ;   if RESET than no code is executed after reset
                                    ;   if STOP,XX then the target executes code for XX period in ms.
                                    ;   if RUN then the target executes code until stopped by the telnet "halt" command
                                    
CORE0_BREAKMODE         = soft      ; default breakpoint mode for the debugger:
                                    ;   soft - use software breakpoints
                                    ;   hard - use hardware breakpoints

CORE_BREAK_PATTERN      = 0xDFFFDFFF ; software breakpoint pattern

CORE0_INIT              = INIT_MX27 ; init section
CORE0_FLASH0            = INTEL_FLASH_P30
CORE0_FLASH1            = FLASH_NAND_BOOT
CORE0_ENDIAN            = little
CORE0_WORKSPACE_ADDR    = 0xa0000000 ; start address of workspace for flash programmer
CORE0_WORKSPACE_LEN     = 0x10000    ; length of workspace in bytes 

CORE0_PATH  = "tftp://192.168.5.1" 

CORE0_FILE  = "test.bin", BIN, 0xA0000000

;-------------------------------------------------
; Init for Freescale M9328MX27ADS board (CPU: M9328MX27)
; memory map:
;   DDR SDRAM - 0xA0000000 - 128 MB
;   Flash     - 0xC0000000 -  32 MB
;   PSRAM     - 0xD6000000 -  16 MB
;
; Caution: 
; On some boards pin.1 and pin.2 of the JTAG connector
; privide different voltages. In a such case please disconnect pin.2
; This is necessary because on the PEEDI's side pin.1 and pin.2 are 
; conencted together.
;
;-------------------------------------------------
[INIT_MX27]
; AHB-Lite IP Interface  
mem write 0x10000000 0x20040304 
mem write 0x10020000 0x00000000 
mem write 0x10000004 0xDFFBFCFB 
mem write 0x10020004 0xFFFFFFFF 

; Set clocks
mem and 0x10027000 0xFFFFFFFC
mem write 0x10027004 0x00331C23
mem write 0x1002700C 0x040C2403
mem write 0x10027000 0x33FF8107
wait 100
mem write 0x10027818 0x00050F08
mem write 0x10027018 0x130410C3
mem write 0x1002701c 0x09030908
mem write 0x10027028 0x00008307
clock normal

; Configure DDR on CSD0 -- initial reset
mem write 0xD8001010 0x00000008

; Configure PSRAM on CS5 
mem write 0xd8002050 0x0000dcf6
mem write 0xd8002054 0x444a4541
mem write 0xd8002058 0x44443302

; Configure 16 bit NorFlash on CS0
mem write 0xd8002000 0x0000CC03
mem write 0xd8002004 0xa0330D01
mem write 0xd8002008 0x00220800

; Configure CPLD on CS4 
mem write 0xd8002040 0x0000DCF6
mem write 0xd8002044 0x444A4541
mem write 0xd8002048 0x44443302

; Configure DDR on CSD0 -- wait 5000 cycle 
mem write 0xD8001010 0x00000008
mem write 0x10027828 0x55555555
mem write 0x10027830 0x55555555
mem write 0x10027834 0x55555555
mem write 0x10027838 0x00005005
mem write 0x1002783C 0x15555555
mem write 0xD8001010 0x00000004
mem write 0xD8001004 0x00795729
mem write 0xD8001000 0x92200000
mem read  0xA0000F00 4  
mem write 0xD8001000 0xA2200000
mem read  0xA0000F00 4  
mem read  0xA0000F00 4  
mem write 0xD8001000 0xB2200000
mem read8 0xA0000033 
mem read8 0xA1000000
mem write 0xD8001000 0x82128485


[U-BOOT]
CHIP                = S29WS256N
ACCESS_METHOD       = AGENT
CHECK_ID            = YES
CHIP_WIDTH          = 16
CHIP_COUNT          = 1
BASE_ADDR           = 0xC0000000
;FILE="tftp:eb9261/u-boot.bin", BIN, 0xC0000000
FILE="card:u-boot.bin", BIN, 0xC0000000
AUTO_ERASE=YES


[INTEL_FLASH_P30]
CHIP			= 28F256P30B
ACCESS_METHOD		= AGENT
CHECK_ID		= YES
CHIP_WIDTH		= 16
CHIP_COUNT		= 1
FILE			= "arm11.bin", 0xA8000000
BASE_ADDR		= 0xC0000000
AUTO_ERASE		= NO
AUTO_LOCK		= NO

[ROOTFS_NAND]
CHIP                = NAND_FLASH
DATA_BASE           = 0xD8000000     ; data
CMD_BASE            = 0x40200000     ; commands (CLE)
ADDR_BASE           = 0x40400000     ; addreses (ALE)
;FILE = "ftp://user:password@192.168.3.1/rootfs.jffs2", BIN, 0
FILE = "card:rootfs.jfs", BIN, 0

; address and value for asserting the Nand Flash Chip select
; [addr] = value
CS_ASSERT   = 0xFFFFF834, 0x4000                

; address and value for releasing the Nand Flash Chip select
; [addr] = value
CS_RELEASE = 0xFFFFF830, 0x4000

; list with bad blocks to be marked as bad
;========================================= 
;BAD_BLOCKS=1146, 1698                  
; CAUTION!!! 
; Enable erasing of bad blocks
; DO NOT Enable this if you don't know what you are doing
; For more information see the AN006 (www.ronetix.at/an006.html)
ERASE_BAD_BLOCKS = NO

OOB_INFO = JFFS2        ; how to deal with the OOB (spare) info
                        ;   RAW   - program 528/2112 bytes from file
                        ;   JFFS2 - program 512/2048 bytes from file and add ECC bytes
                        ;   FF    - program 512/2048 bytes from file, set spare info to 0xFF    

[FLASH_NAND_BOOT]
CHIP                = NAND_FLASH
CPU		    = iMX27
FILE = "card:rootfs.jfs", BIN, 0
ERASE_BAD_BLOCKS = NO
OOB_INFO = IMX_ECC

[SERIAL]
BAUD=115200
STOP_BITS=1
PARITY=NONE
TCP_PORT = 0 ; 2023

[TELNET]
PROMPT = "mx27> "                   ; telnet prompt
;BACKSPACE=127                      ; comment out for autodetect

[DISPLAY]
BRIGHTNESS      = 20                ; LED indicator brightness
VOLUME          = 25                ; beeper volume


[ACTIONS]                           ; user defined scripts
;AUTORUN        = 1                 ; executed on every target connect
1 = loadredboot
2 = flashredboot
3 = erase
4 = progall
5 = dump_ram
6 = dump_flash

[loadredboot]
halt
memory load tftp://192.168.5.1/redboot.bin bin 0xa0000000
go 0xa0000000

[flashredboot]
halt
flash program tftp://192.168.5.1/redboot.bin bin 0xc0000000 erase
go 0xc0000000

[erase]                             ; erase flash
flash erase

[progall]                              ; program flash
flash set 0
flash prog                          ; program U-BOOT
flash set 1
flash prog                          ; program kernel
flash set 2
flash erase                         ; erase NAND Flash
flash prog                          ; program rootfs

[dump_ram]                          ; dump part of RAM
memory dump 0x20000000 0x0100 card:ram.bin

[dump_flash]
flash dump 0xc0000000 0x2000000 tftp://192.168.5.1/flashdump
</pre>

[[Category:i.MX27]]