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PEEDI Configuration (i.MX 27) - Versionsgeschichte
2026-05-13T14:12:42Z
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Peter: 1 Version importiert
2023-10-31T08:03:09Z
<p>1 Version importiert</p>
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Peter
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en>Peter: 1 Version importiert
2023-08-22T19:35:52Z
<p>1 Version importiert</p>
<p><b>Neue Seite</b></p><div>The PEEDI JTAG supports the CM-i.MX27 core module.<br />
<br />
If you want to use the PEEDI JTAG, be sure that no software has executed before on the processor, otherwise PEEDI will not be able to connect. So, set the boot mode to '''0000''' (UART/USB bootstrapping). This way, nothing from flash is executed.<br />
<br />
You will see the following in the PEEDI terminal:<br />
++ info: RESET and TRST asserted<br />
++ info: TRST released<br />
-- error: wrong number of TAP controller(s): detected = 0, config = 2<br />
++ info: BYPASS check failed<br />
<br />
++ info: RESET released, trying again<br />
++ info: BYPASS check passed<br />
++ info: 2 TAP controller(s) detected<br />
++ info: TAP 0 : IDCODE = 0x07926121, Freescale i.MX27 -> CORE0<br />
++ info: TAP 1 : IDCODE = 0x1B900F0F, ARM ETB<br />
Configuring for CM-i.MX27...<br />
<br />
Set clocks...<br />
<br />
<br />
Configure DDR...<br />
<br />
<br />
0xA0000F00: 0x00000000 0x00000000 0x00000000 0x00000000<br />
<br />
0xA0000F00: 0x00000000 0x00000000 0x00000000 0x00000000<br />
<br />
0xA0000F00: 0x00000000 0x00000000 0x00000000 0x00000000<br />
<br />
0xA0000033: 0x00<br />
<br />
0xA1000000: 0x00<br />
Initialization complete.<br />
<br />
++ info: core 0: initialized<br />
<br />
The following is an example configuration for PEEDI when used with the CM-i.MX27.<br />
<br />
<pre><br />
[DEBUGGER]<br />
PROTOCOL = gdb_remote ; gdb remote<br />
REMOTE_PORT = 2000 ; TCP/IP port<br />
GDB_READ_INGNORE_TIME = 3000 ; time in ms<br />
<br />
[TARGET]<br />
PLATFORM = ARM<br />
<br />
[PLATFORM_ARM]<br />
JTAG_CHAIN = 4, 4 ; list of IR lenghts of all TAP controller in JTAG chain<br />
JTAG_CLOCK = 5, 10000 ; JTAG Clock in [kHz] - 5kHz jtag clock for init operations and 10MHz for normal work<br />
; Valid range: 5 - 33000<br />
TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL<br />
WAKEUP_TIME = 3000 ; time between releasing the reset and starting the jtag communication<br />
RESET_TIME = 500 ; lenght of RESET pulse in ms; 0 means no RESET<br />
<br />
CORE0 = ARM926E, 0 ; TAP 0 is ARM926E CPU<br />
CORE0_STARTUP_MODE = RESET ; startup mode after reset:<br />
; if RESET than no code is executed after reset<br />
; if STOP,XX then the target executes code for XX period in ms.<br />
; if RUN then the target executes code until stopped by the telnet "halt" command<br />
<br />
CORE0_BREAKMODE = soft ; default breakpoint mode for the debugger:<br />
; soft - use software breakpoints<br />
; hard - use hardware breakpoints<br />
<br />
CORE_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern<br />
<br />
CORE0_INIT = INIT_MX27 ; init section<br />
CORE0_FLASH0 = INTEL_FLASH_P30<br />
CORE0_FLASH1 = FLASH_NAND_BOOT<br />
CORE0_ENDIAN = little<br />
CORE0_WORKSPACE_ADDR = 0xa0000000 ; start address of workspace for flash programmer<br />
CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes <br />
<br />
CORE0_PATH = "tftp://192.168.5.1" <br />
<br />
CORE0_FILE = "test.bin", BIN, 0xA0000000<br />
<br />
;-------------------------------------------------<br />
; Init for Freescale M9328MX27ADS board (CPU: M9328MX27)<br />
; memory map:<br />
; DDR SDRAM - 0xA0000000 - 128 MB<br />
; Flash - 0xC0000000 - 32 MB<br />
; PSRAM - 0xD6000000 - 16 MB<br />
;<br />
; Caution: <br />
; On some boards pin.1 and pin.2 of the JTAG connector<br />
; privide different voltages. In a such case please disconnect pin.2<br />
; This is necessary because on the PEEDI's side pin.1 and pin.2 are <br />
; conencted together.<br />
;<br />
;-------------------------------------------------<br />
[INIT_MX27]<br />
; AHB-Lite IP Interface <br />
mem write 0x10000000 0x20040304 <br />
mem write 0x10020000 0x00000000 <br />
mem write 0x10000004 0xDFFBFCFB <br />
mem write 0x10020004 0xFFFFFFFF <br />
<br />
; Set clocks<br />
mem and 0x10027000 0xFFFFFFFC<br />
mem write 0x10027004 0x00331C23<br />
mem write 0x1002700C 0x040C2403<br />
mem write 0x10027000 0x33FF8107<br />
wait 100<br />
mem write 0x10027818 0x00050F08<br />
mem write 0x10027018 0x130410C3<br />
mem write 0x1002701c 0x09030908<br />
mem write 0x10027028 0x00008307<br />
clock normal<br />
<br />
; Configure DDR on CSD0 -- initial reset<br />
mem write 0xD8001010 0x00000008<br />
<br />
; Configure PSRAM on CS5 <br />
mem write 0xd8002050 0x0000dcf6<br />
mem write 0xd8002054 0x444a4541<br />
mem write 0xd8002058 0x44443302<br />
<br />
; Configure 16 bit NorFlash on CS0<br />
mem write 0xd8002000 0x0000CC03<br />
mem write 0xd8002004 0xa0330D01<br />
mem write 0xd8002008 0x00220800<br />
<br />
; Configure CPLD on CS4 <br />
mem write 0xd8002040 0x0000DCF6<br />
mem write 0xd8002044 0x444A4541<br />
mem write 0xd8002048 0x44443302<br />
<br />
; Configure DDR on CSD0 -- wait 5000 cycle <br />
mem write 0xD8001010 0x00000008<br />
mem write 0x10027828 0x55555555<br />
mem write 0x10027830 0x55555555<br />
mem write 0x10027834 0x55555555<br />
mem write 0x10027838 0x00005005<br />
mem write 0x1002783C 0x15555555<br />
mem write 0xD8001010 0x00000004<br />
mem write 0xD8001004 0x00795729<br />
mem write 0xD8001000 0x92200000<br />
mem read 0xA0000F00 4 <br />
mem write 0xD8001000 0xA2200000<br />
mem read 0xA0000F00 4 <br />
mem read 0xA0000F00 4 <br />
mem write 0xD8001000 0xB2200000<br />
mem read8 0xA0000033 <br />
mem read8 0xA1000000<br />
mem write 0xD8001000 0x82128485<br />
<br />
<br />
[U-BOOT]<br />
CHIP = S29WS256N<br />
ACCESS_METHOD = AGENT<br />
CHECK_ID = YES<br />
CHIP_WIDTH = 16<br />
CHIP_COUNT = 1<br />
BASE_ADDR = 0xC0000000<br />
;FILE="tftp:eb9261/u-boot.bin", BIN, 0xC0000000<br />
FILE="card:u-boot.bin", BIN, 0xC0000000<br />
AUTO_ERASE=YES<br />
<br />
<br />
[INTEL_FLASH_P30]<br />
CHIP = 28F256P30B<br />
ACCESS_METHOD = AGENT<br />
CHECK_ID = YES<br />
CHIP_WIDTH = 16<br />
CHIP_COUNT = 1<br />
FILE = "arm11.bin", 0xA8000000<br />
BASE_ADDR = 0xC0000000<br />
AUTO_ERASE = NO<br />
AUTO_LOCK = NO<br />
<br />
[ROOTFS_NAND]<br />
CHIP = NAND_FLASH<br />
DATA_BASE = 0xD8000000 ; data<br />
CMD_BASE = 0x40200000 ; commands (CLE)<br />
ADDR_BASE = 0x40400000 ; addreses (ALE)<br />
;FILE = "ftp://user:password@192.168.3.1/rootfs.jffs2", BIN, 0<br />
FILE = "card:rootfs.jfs", BIN, 0<br />
<br />
; address and value for asserting the Nand Flash Chip select<br />
; [addr] = value<br />
CS_ASSERT = 0xFFFFF834, 0x4000 <br />
<br />
; address and value for releasing the Nand Flash Chip select<br />
; [addr] = value<br />
CS_RELEASE = 0xFFFFF830, 0x4000<br />
<br />
; list with bad blocks to be marked as bad<br />
;========================================= <br />
;BAD_BLOCKS=1146, 1698 <br />
; CAUTION!!! <br />
; Enable erasing of bad blocks<br />
; DO NOT Enable this if you don't know what you are doing<br />
; For more information see the AN006 (www.ronetix.at/an006.html)<br />
ERASE_BAD_BLOCKS = NO<br />
<br />
OOB_INFO = JFFS2 ; how to deal with the OOB (spare) info<br />
; RAW - program 528/2112 bytes from file<br />
; JFFS2 - program 512/2048 bytes from file and add ECC bytes<br />
; FF - program 512/2048 bytes from file, set spare info to 0xFF <br />
<br />
[FLASH_NAND_BOOT]<br />
CHIP = NAND_FLASH<br />
CPU = iMX27<br />
FILE = "card:rootfs.jfs", BIN, 0<br />
ERASE_BAD_BLOCKS = NO<br />
OOB_INFO = IMX_ECC<br />
<br />
[SERIAL]<br />
BAUD=115200<br />
STOP_BITS=1<br />
PARITY=NONE<br />
TCP_PORT = 0 ; 2023<br />
<br />
[TELNET]<br />
PROMPT = "mx27> " ; telnet prompt<br />
;BACKSPACE=127 ; comment out for autodetect<br />
<br />
[DISPLAY]<br />
BRIGHTNESS = 20 ; LED indicator brightness<br />
VOLUME = 25 ; beeper volume<br />
<br />
<br />
[ACTIONS] ; user defined scripts<br />
;AUTORUN = 1 ; executed on every target connect<br />
1 = loadredboot<br />
2 = flashredboot<br />
3 = erase<br />
4 = progall<br />
5 = dump_ram<br />
6 = dump_flash<br />
<br />
[loadredboot]<br />
halt<br />
memory load tftp://192.168.5.1/redboot.bin bin 0xa0000000<br />
go 0xa0000000<br />
<br />
[flashredboot]<br />
halt<br />
flash program tftp://192.168.5.1/redboot.bin bin 0xc0000000 erase<br />
go 0xc0000000<br />
<br />
[erase] ; erase flash<br />
flash erase<br />
<br />
[progall] ; program flash<br />
flash set 0<br />
flash prog ; program U-BOOT<br />
flash set 1<br />
flash prog ; program kernel<br />
flash set 2<br />
flash erase ; erase NAND Flash<br />
flash prog ; program rootfs<br />
<br />
[dump_ram] ; dump part of RAM<br />
memory dump 0x20000000 0x0100 card:ram.bin<br />
<br />
[dump_flash]<br />
flash dump 0xc0000000 0x2000000 tftp://192.168.5.1/flashdump<br />
</pre><br />
<br />
[[Category:i.MX27]]</div>
en>Peter